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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVC2G07GN

Buffers with open-drain outputs

The 74LVC2G07 is a dual buffer with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • -24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類型

型號 VCC (V) Logic switching levels Output drive capability (mA) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Rth(j-c) (K/W) Package name
74LVC2G07GN 1.65?-?5.5 CMOS/LVTTL 32 175 2 low -40~125 274 170 XSON6

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC2G07GN 74LVC2G07GN,132
(935291801132)
Active V7 SOT1115
XSON6
(SOT1115)
SOT1115 REFLOW_BG-BD-1
SOT1115_132

環(huán)境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVC2G07GN 74LVC2G07GN,132 74LVC2G07GN rohs rhf rhf
品質及可靠性免責聲明

文檔 (12)

文件名稱 標題 類型 日期
74LVC2G07 Buffers with open-drain outputs Data sheet 2023-08-28
AN11009 Pin FMEA for LVC family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT1115 3D model for products with SOT1115 package Design support 2023-02-02
lvc2g07 74LVC2G07 IBIS model IBIS model 2015-09-06
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
XSON6_SOT1115_mk plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 0.9 mm x 1 mm x 0.35 mm body Marcom graphics 2017-01-28
SOT1115 plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm body Package information 2022-05-27
SOT1115_132 XSON6; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-04-21
74LVC2G07GN_Nexperia_Product_Reliability 74LVC2G07GN Nexperia Product Reliability Quality document 2024-06-16
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT1115 MAR_SOT1115 Topmark Top marking 2013-06-03

支持

如果您需要設計/技術支持,請告知我們并填寫 應答表 我們會盡快回復您。

模型

文件名稱 標題 類型 日期
lvc2g07 74LVC2G07 IBIS model IBIS model 2015-09-06
SOT1115 3D model for products with SOT1115 package Design support 2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74LVC2G07GN 74LVC2G07GN,132 935291801132 Active SOT1115_132 5,000 訂單產品

樣品

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如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網絡可為您提供 Nexperia 樣品支持。查看官方經銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74LVC2G07GN 74LVC2G07GN,132 935291801132 SOT1115 訂單產品
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