可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74HC74BQ | 74HC74BQ,115 | 935273672115 | SOT762-1 | 訂單產(chǎn)品 |
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Click here for more information74HC74BQ
Dual D-type flip-flop with set and reset; positive edge-trigger
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Alternatives
Features and benefits
- Wide supply voltage range from 2.0 to 6.0 V
- CMOS low power dissipation
- High noise immunity
Input levels:
For 74HC74: CMOS level
For 74HCT74: TTL level
Symmetrical output impedance
High noise immunity
Balanced propagation delays
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
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Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC74BQ | 2.0?-?6.0 | CMOS | ± 5.2 | 14 | 82 | low | -40~125 | 106 | 20.9 | 74 | DHVQFN14 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC74BQ | 74HC74BQ,115 (935273672115) |
Active | HC74 |
DHVQFN14 (SOT762-1) |
SOT762-1 | SOT762-1_115 |
Series
文檔 (11)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74HC_HCT74 | Dual D-type flip-flop with set and reset; positive edge-trigger | Data sheet | 2024-04-02 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| SOT762-1 | 3D model for products with SOT762-1 package | Design support | 2019-10-03 |
| hc74 | 74HC74 IBIS model | IBIS model | 2022-10-21 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN14_SOT762-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; 0.5 mm pitch; 2.5 mm x 3 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| SOT762-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 14 terminals; 0.5 mm pitch; 2.5 x 3 x 1 mm body | Package information | 2023-04-05 |
| SOT762-1_115 | DHVQFN14; Reel pack for SMD, 7"; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74HC74BQ_Nexperia_Product_Reliability | 74HC74BQ Nexperia Product Reliability | Quality document | 2024-06-16 |
| hc | HC/HCT Spice model | SPICE model | 2022-02-17 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請告知我們并填寫 應(yīng)答表 我們會盡快回復(fù)您。
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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訂購、定價(jià)與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74HC74BQ | 74HC74BQ,115 | 935273672115 | Active | SOT762-1_115 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74HC74BQ
Dual D-type flip-flop with set and reset; positive edge-trigger
從安世半導(dǎo)體購買
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