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Click here for more information74AUP2G241GM
Low-power dual buffer/line driver; 3-state
The 74AUP2G241 provides a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This device has an input-disable feature, which allows floating input signals. The input 1A is disabled when the output enable input 1OE is HIGH. The input 2A is disabled when the output enable input 2OE is LOW.
Alternatives
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
Input-disable feature allows floating input conditions
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | Package name |
|---|---|
| 74AUP2G241GM | XQFN8 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP2G241GM | 74AUP2G241GM,125 (935281438125) |
Obsolete | p41 |
XQFN8 (SOT902-2) |
SOT902-2 | SOT902-2_125 |
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP2G241GM | 74AUP2G241GM,125 | 74AUP2G241GM |
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Series
文檔 (9)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP2G241 | Low-power dual buffer/line driver; 3-state | Data sheet | 2023-07-27 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| aup2g241 | aup2g241 IBIS model | IBIS model | 2013-04-07 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| XQFN8_SOT902-2_mk | plastic, extremely thin quad flat package; 8 terminals; 0.55 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| SOT902-2 | plastic, leadless extremely thin quad flat package; 8 terminals; 0.5 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body | Package information | 2020-04-21 |
支持
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模型
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| aup2g241 | aup2g241 IBIS model | IBIS model | 2013-04-07 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AUP2G241GM
Low-power dual buffer/line driver; 3-state
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